The present invention relates to a dynamic RAM (Random Access Memory) and, more particularly, to a technique which is effective when applied to a word line selecting technique in a synchronous dynamic RAM (hereinafter simply referred to as the "SDRAM").
When the high level of a bit line is written in a dynamic memory cell composed of a memory capacitor and an address select MOSFET, the select level of a word line has to be raised to a high level, which is made higher by the threshold voltage of the address select MOSFET than the high level of the bit line. In accordance with the trend toward microminiaturization of elements, the gate oxide film of the address select MOSFET is thinned, causing a problem with regard to the field intensity of the gate oxide film. In order to prevent aging dielectric breakdown of the gate oxide film, there has been described in Japanese Patent Laid-Open No. 1-162296/1989 a technique in which the select level of the word line is raised to the boosted voltage for a precharge period after the end of an Address Strobe (AS) cycle.
Moreover, the boosting of the voltage of the word line is disclosed in Japanese Utility Model Laid-Open Nos. 62-171095/1987 and 63-13498/1988, Japanese Patent Laid-Open Nos. 2-247892/1990, 4-42494/1992, 5-151773/1993, 62-501807/1987, 63-255897/1988, 8-129884/1995, and 5-89673/1993.